In wired communication the clock, i.e., the timing information, is extracted from the received data signal, including both frequency and phase of the clock. In applications where provision of an accurate clock is not affordable, the initial frequency of the receiver can be substantially far from the clock frequency used for transmission of data. In this case, frequency locking becomes a difficult and important task. A typical receiver also needs to perform channel equalization to control and cancel inter-symbol-interference caused by the signal propagation media. Channel equalization can be performed by Continuous Time Linear Equalization (CTLE) followed by a non-linear Decision Feedback Equalization (DFE). While CTLE does not require a clock, any form of DFE needs a reliable clock to operate properly. Accordingly, in the initial frequency acquisition stage the Clock Data Recovery (CDR) function can only benefit from CTLE equalization. Given this background, the design of CTLE faces two different requirements: a first requirement imposed by the CDR frequency acquisition needs and a second requirement imposed by final data detection performance that requires CTLE to be jointly optimized with operation of the DFE stage. These two requirements are difficult to meet in a single CTLE design, as CDR demands a high level of equalization by CTLE in order to lock frequency during an initial stage while a high level of CTLE equalization is not efficient for DFE operation.